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rtl8212-gr RTL8212N-GR rtl8211n-gr integrated 10/100/1000 single/dual gigabit ethernet transceiver datasheet rev. 1.3 03 august 2007 track id: jatr-1076-21 realtek semiconductor corp. no. 2, innovation road ii, hsinchu science park, hsinchu 300, taiwan tel.: +886-3-578-0211. fax: +886-3-577-6047 www.realtek.com.tw www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver ii track id: jatr-1076-21 rev. 1.3 copyright ?2007 realtek semiconductor corp. all rights reserved. no part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of realtek semiconductor corp. disclaimer realtek provides this document ?as is?, without warranty of any kind, neither expressed nor implied, including, but not limited t o, the particular pu rpose. realtek may make impr ovements and/or changes in this document or in the product described in this document at any time. this document could include technical inaccuracies or typographical errors. trademarks realtek is a trademark of realtek semiconductor co rporation. other names mentioned in this document are trademarks/registered trademarks of their respective owners. using this document this document is intended for the hardware and soft ware engineer?s general information on the realtek rtl8212/rtl8212n/rtl8211n integrated circuits. though every effort has been made to ensure that th is document is current and accurate, more information may have become available subsequent to the production of this guide. in that ev ent, please contact your realtek representative for additional information that may help in the development process. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver iii track id: jatr-1076-21 rev. 1.3 revision history revision release date summary 1.0 2005/08/10 first release. 1.1 2005/09/09 1. add rtl8211n-gr single phyceiver. 2. correct typo for page 20 p0rxdv description. 1.2 2005/11/15 1. update datasheet and product name to rtl8212, rtl8212n and rtl8211n. 2. remove rsgmii interface from rtl8212 (qfp-128). 1.3 2007/08/03 1. describe clkin signal in detail for rtl8212 dhs-qfp128 application (table 10 system clock interface pins, page 14). 2. correct rgmii revision number (section 7.2.1 reduced gmii (rgmii), page 23). 3. correct typo for mdc cl ock operation frequency (section 7.4 mdc/mdio manage ment interface, page 32). 4. update temperature ratings in section 8.1 and 8.2, page 46. 5. update gmii mode timing (rxc and rxd parameters). add gtxc cycle time parameters. add rxc time high/low and rxc rise/fall time parameters (table 49 digital timing characteristics, page 49). 6. update rgmii mode timing (rxc parameters) add clock output skew data) update led timing parameters (table 49 digital timing characteristics, page 49). 7. add section 8.5 thermal , page 50. 8. change rtl8212 package from edhs-qfp-128 to dhs-qfp-128 (section 10.1 dhs-qfp-128 dimensions (rtl8212), page 55). www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver iv track id: jatr-1076-21 rev. 1.3 table of contents 1. general description ............................................................................................................ ..................................1 2. features ....................................................................................................................... ..................................................2 3. system applications ............................................................................................................ ...................................3 3.1. s ystem a pplication d iagrams ............................................................................................................................... .3 4. block diagram .................................................................................................................. .........................................4 5. pin assignments................................................................................................................ ..........................................5 5.1. rtl8212 dhs-qfp-128 p ackage .............................................................................................................................5 5.2. p ackage i dentification (rtl8212 dhs-qfp-128) ................................................................................................5 5.3. rtl8212n qfn-76 p ackage ............................................................................................................................... ......6 5.4. p ackage i dentification (rtl8212n qfn-76)........................................................................................................6 5.5. rtl8211n qfn-76 p ackage ............................................................................................................................... ......7 5.6. p ackage i dentification (rtl8211n qfn-76) ........................................................................................................7 6. pin descriptions............................................................................................................... ..........................................8 6.1. m edia d ependent i nterface p ins ...........................................................................................................................8 6.2. mii/gmii t ransmit i nterface p ins ........................................................................................................................9 6.3. mii/gmii r eceive i nterface p ins .........................................................................................................................10 6.4. rgmii t ransmit i nterface p ins ...........................................................................................................................11 6.5. rgmii r eceive i nterface p ins ..............................................................................................................................1 2 6.6. rsgmii i nterface p ins ............................................................................................................................... ...........12 6.7. s erial m anagement i nterface p ins ....................................................................................................................13 6.8. s erial led i nterface p ins ............................................................................................................................... .....13 6.9. s ystem c lock i nterface p ins ............................................................................................................................... 14 6.10. c onfiguration and c ontrol p ins .........................................................................................................................15 6.11. m iscellaneous p ins ............................................................................................................................... ................16 6.12. p ower and g round p ins ............................................................................................................................... .........17 7. functional description ......................................................................................................... ............................18 7.1. mdi i nterface ............................................................................................................................... ..........................18 7.1.1. crossover detection an d auto correction........................................................................................ ....................18 www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver v track id: jatr-1076-21 rev. 1.3 7.1.2. polarity co rrection............................................................................................................ ...................................19 7.1.3. mac inte rface .................................................................................................................. ....................................20 7.2. g igabit m edia i ndependent i nterface (mii/gmii) ............................................................................................21 7.2.1. reduced gmii (rgmii) ........................................................................................................... ............................23 7.2.2. 10/100mbps f unctiona lity....................................................................................................... .............................24 7.2.3. tx_ctl and rx _ctl co ding....................................................................................................... .......................25 7.2.4. in-band status ................................................................................................................. .....................................27 7.2.5. four rgmii modes ............................................................................................................... ...............................27 7.3. r educed s erial gmii (rtl8212n and rtl8211n o nly ) ...................................................................................28 7.3.1. rsgmii data transfer ........................................................................................................... ..............................30 7.4. mdc/mdio m anagement i nterface ...................................................................................................................32 7.4.1. preamble sup pressi on ........................................................................................................... ...............................33 7.5. h ardware c onfiguration i nterface ...................................................................................................................34 7.6. led c onfiguration ............................................................................................................................... .................35 7.6.1. led system applic ation examples ................................................................................................ ......................35 7.6.2. serial stream order............................................................................................................ ..................................36 7.7. s ystem c lock i nterface ............................................................................................................................... ........36 7.8. r egister d escriptions ............................................................................................................................... ............37 7.8.1. register symbols ............................................................................................................... ...................................37 7.8.2. mii specification de fined regi sters............................................................................................ .........................37 7.8.3. register0: control ............................................................................................................. ...................................38 7.8.4. register1: status.............................................................................................................. .....................................39 7.8.5. register2: phy id entifier 1 re gister ........................................................................................... .........................40 7.8.6. register3: phy id entifier 2 re gister ........................................................................................... .........................40 7.8.7. register4: auto-nego tiation adver tisement ...................................................................................... ...................41 7.8.8. register5: auto-negotia tion link pa rtner ability ............................................................................... .................42 7.8.9. register6: auto-ne gotiation expansion .......................................................................................... .....................43 7.8.10. register7: auto-negotiatio n page transm it regi ster............................................................................. .........43 7.8.11. register8: auto-negotiation link partner next page register .................................................................... ...44 7.8.12. register9: 1000base-t control register ......................................................................................... ................44 7.8.13. register10: 1000base- t status register......................................................................................... .................45 7.8.14. register15: extended status .................................................................................................... ........................45 8. characteristics................................................................................................................ ......................................46 8.1. a bsolute m aximum r at i n g s ............................................................................................................................... ..46 8.2. o perating r ange ............................................................................................................................... .....................46 www.datasheet.co.kr datasheet pdf - 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rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver vi track id: jatr-1076-21 rev. 1.3 8.3. dc c haracteristics ............................................................................................................................... ................47 8.4. ac c haracteristics ............................................................................................................................... ................48 8.4.1. mii interface data timing...................................................................................................... ..............................48 8.4.2. digital timing c haracteristics ................................................................................................. ............................49 8.5. t hermal c haracteristics ............................................................................................................................... ......50 8.5.1. qfn-76 therma l parameters...................................................................................................... .........................51 8.5.2. qfn-76 thermal operating range................................................................................................. .....................51 8.5.3. dhs-qfp-128 ther mal parameters ................................................................................................. ...................51 8.5.4. dhs-qfp-128 thermal operating range ............................................................................................ ...............51 9. design and layout guide ........................................................................................................ ............................52 9.1. g eneral g uidelines ............................................................................................................................... ................52 9.2. mii/gmii/rgmii s ignal l ayout g uidelines .......................................................................................................52 9.3. rsgmii s ignal l ayout g uidelines ......................................................................................................................53 9.4. e thernet mdi d ifferential s ignal l ayout g uidelines ...................................................................................53 9.5. c lock c ircuit ............................................................................................................................... ..........................53 9.6. p ower p lanes ............................................................................................................................... ...........................53 9.7. g round p lane ............................................................................................................................... ..........................54 9.8. t ransformer o ptions ............................................................................................................................... .............54 10. mechanical dimensions.......................................................................................................... ............................55 10.1. dhs-qfp-128 d imensions (rtl8212) ...................................................................................................................55 10.2. n otes f or dhs-qfp-128 d imensions (rtl8212) ................................................................................................56 10.3. qfn-76 d imensions (rtl8211n & rtl8212n) ....................................................................................................57 10.4. n otes f or qfn-76 d imensions (rtl8211n & rtl8212n) .................................................................................58 11. ordering information ........................................................................................................... .............................59 www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver vii track id: jatr-1076-21 rev. 1.3 list of tables t able 1. p in t ype a bbreviations ............................................................................................................................... .............8 t able 2. m edia d ependent i nterface p ins ...........................................................................................................................8 t able 3. mii/gmii t ransmit i nterface p ins .........................................................................................................................9 t able 4. mii/gmii r eceive i nterface p ins .........................................................................................................................10 t able 5. rgmii t ransmit i nterface p ins ...........................................................................................................................11 t able 6. rgmii r eceive i nterface p ins ..............................................................................................................................1 2 t able 7. rsgmii i nterface p ins ............................................................................................................................... ...........12 t able 8. s erial m anagement i nterface p ins .....................................................................................................................13 t able 9. s erial led i nterface p ins ............................................................................................................................... .....13 t able 10. s ystem c lock i nterface p ins ............................................................................................................................... 14 t able 11. c onfiguration and c ontrol p ins ........................................................................................................................15 t able 12. m iscellaneous p ins ............................................................................................................................... ................16 t able 13. p ower and g round p ins ............................................................................................................................... .........17 t able 14. m apping of t wisted -p air o utputs to rj-45 c onnectors .................................................................................18 t able 15. m edia d ependent i nterface p in m apping ...........................................................................................................18 t able 16. d ata r at e s s upported t hrough e ach i nterface ...............................................................................................20 t able 17. mac i nterface m odes of o peration ...................................................................................................................20 t able 18. g igabit m edia i ndependent i nterface ................................................................................................................21 t able 19. mac i nterface m odes of o peration ...................................................................................................................23 t able 20. tx_er and tx_en e ncoding ............................................................................................................................... 25 t able 21. rx_er and rx_dv e ncoding ..............................................................................................................................2 6 t able 22. rgmii t iming m odes ............................................................................................................................... ..............27 t able 23. c onfiguration p in d efinitions .............................................................................................................................34 t able 24. led m ode ............................................................................................................................... .................................35 t able 25. led s tatus ............................................................................................................................... ...............................35 t able 26. s erial s tream o rder (m ode 0) ............................................................................................................................3 6 t able 27. s erial s tream o rder (m ode 1) ............................................................................................................................3 6 t able 28. mii s pecification d efined r egisters ...................................................................................................................37 t able 29. r egister 0: c ontrol ............................................................................................................................... ................38 t able 30. r egister 1: s tatus ............................................................................................................................... ....................39 t able 31. r egister 2: phy i dentifier 1 r egister .................................................................................................................40 t able 32. r egister 3: phy i dentifier 2 r egister .................................................................................................................40 www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver viii track id: jatr-1076-21 rev. 1.3 t able 33. r egister 4: a uto -n egotiation a dvertisement ...................................................................................................41 t able 34. r egister 5: a uto -n egotiation l ink p artner a bility ........................................................................................42 t able 35. r egister 6: a uto -n egotiation e xpansion ...........................................................................................................43 t able 36. r egister 7: a uto -n egotiation p age t ransmit r egister ...................................................................................43 t able 37. r egister 8: a uto -n egotiation l ink p artner n ext p age r egister ...................................................................44 t able 38. r egister 9: 1000b ase -t c ontrol r egister ..........................................................................................................44 t able 39. r egister 10: 1000b ase -t s tatus r egister ...........................................................................................................45 t able 40. r egister 15: e xtended s tatus ............................................................................................................................... 45 t able 41. a bsolute m aximum r at i n g s ............................................................................................................................... ..46 t able 42. o perating r ange ............................................................................................................................... .....................46 t able 43. dc c haracteristics ............................................................................................................................... ................47 t able 44. d igital t iming c haracteristics ..........................................................................................................................49 t able 45. qfn-76 t hermal p arameters ............................................................................................................................... 51 t able 46. qfn-76 t hermal o perating r ange .....................................................................................................................51 t able 47. dhs-qfp-128 t hermal p arameters ....................................................................................................................51 t able 48. dhs-qfp-128 t hermal o perating r ange ...........................................................................................................51 t able 49. o rdering i nformation ............................................................................................................................... ...........59 www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver ix track id: jatr-1076-21 rev. 1.3 list of figures f igure 1. rtl8212n with 8-p ort g igabit mac (rtl8369).................................................................................................3 f igure 2. rtl8212 with 24+2g mac (rtl8326)...................................................................................................................3 f igure 3. b lock d iagram ............................................................................................................................... ........................4 f igure 4. p in a ssignments (rtl8212 dhs-qfp-128) ...........................................................................................................5 f igure 5. p in a ssignments (rtl8212n qfn-76)...................................................................................................................6 f igure 6. p in a ssignments (rtl8211n qfn-76)...................................................................................................................7 f igure 7. c onceptual e xample of p olarity c orrection ................................................................................................19 f igure 8. gmii s ignal d iagram ............................................................................................................................... ............21 f igure 9. mii s ignal d iagram ............................................................................................................................... ...............22 f igure 10. rgmii s ignal d iagram ............................................................................................................................... .........24 f igure 11. rgmii d ata t ransmission ............................................................................................................................... ....25 f igure 12. rgmii d ata r eception w ithout e rror .............................................................................................................26 f igure 13. rgmii d ata r eception w ith e rror ...................................................................................................................26 f igure 14. rsgmii i nterconnection d iagram ...................................................................................................................28 f igure 15. r ealtek 8g s witch a pplication with rsgmii..................................................................................................29 f igure 16. rsgmii f unctional b lock d iagram at e thernet phy s ide ..........................................................................31 f igure 17. rsgmii f unctional b lock d iagram at e thernet mac s ide .........................................................................31 f igure 18. mdio r ead f rame f ormat ............................................................................................................................... ...33 f igure 19. mdio w rite f rame f ormat ............................................................................................................................... .33 f igure 20. c lock g enerated from mac (rsgmii m ode )..................................................................................................36 f igure 21. mii i nterface r eception d ata t iming ...............................................................................................................48 f igure 22. mii i nterface t ransmission d ata t iming ..........................................................................................................48 www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 1 track id: jatr-1076-21 rev. 1.3 1. general description the rtl8212/rtl8212n/8211n integrate dual/single inde pendent gigabit ethernet transceivers into a single ic and perform all the physical layer (phy) functions for 10base-t, 100base-tx, and 1000base-t ethernet on category 3 (10base-t) or category 5 utp cable (except 1000 base-t half duplex operation). the devices include the pcs, pma, and pmd sub-la yers. they perform enc oding/decoding, clock/data recovery, digital adap tive equalization, echo cancelle rs, cross-talk elimination, line driver, as well as all other required support circu it functions. the devices also integrate an internal hybrid that allows the use of inexpensive 1:1 transformer modules. each of the two independent transceivers featur es an industrial standard mii, gmii, and rgmii (reduced gigabit media independent interface). to further reduce pcb trace complexity, the rtl8211n/8212n also provides an innovative 2.5gbps se rial interface ? the reduced serial gigabit media independent interface (rsgmii). both dual tran sceivers can simultaneous ly communicate with the mac through the same rsgmii interface. the rtl8212/rtl8212n/8211n adopts mixed mode 0.13 m cmos technology and analog line driver architecture that offers lower power consumption than dac architecture. two package types are available; a thermally-enha nced 128-pin dhs-qfp (drop-in heat sink qfp) package, and a 76-pin qfn (quad flat no-lead) package. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 2 track id: jatr-1076-21 rev. 1.3 2. features ? single/dual integrated 10/100/1000base- t gigabit ethernet transceiver ? supports full duplex at 10/100/1000mbps, and half duplex at 10/100mbps ? supports 2.5v i/o (3.3v input tolerance) gmii and rgmii inte rfaces in 10/100/1000 mode for rtl8212 (dhs-qfp-128 package) ? supports rsgmii (2.5gbps serial high sp eed interface) in 10/100/1000 mode for rtl8212n and rtl8211n (qfn-76 package) ? crossover detection and auto correction at all 3 speeds ? automatic detection and correction of wiring pair swaps, pair sk ew, and pair polarity ? supports serial led mode ? line driver architecture with lo w power dissipation pave=0.78w/port ? 3.3v, 1.8v, and 1.2v power supply (2.5v is generated by internal linear regulator for digital i/o pads) ? packages: ? rtl8212: dhs-qfp-128, 14x20mm, 0.5mm lead pitch package ? rtl8212n and rtl8211n: qfn-76, 9x9mm, 0.4mm pitch package ? 0.13m cmos process www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 3 track id: jatr-1076-21 rev. 1.3 3. system applications high-density gigabit ethernet switches and routers 3.1. system application diagrams figure 1. rtl8212n with 8-port gigabit mac (rtl8369) rtl8326 24+2g ethernet mac magnetics rj-45 rtl8208 octa - phy ( 10/100 ) rtl8212 dual - phy ( 10/100/1000 ) rj-45 mac interface : gmii/mii - rgmii rtl8208 octa - phy ( 10/100 ) rtl8208 octa - phy ( 10/100 ) rj- 45 * 8 rj- 45 * 8 rj- 45 * 8 figure 2. rtl8212 with 24+2g mac (rtl8326) www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 4 track id: jatr-1076-21 rev. 1.3 4. block diagram figure 3. block diagram www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 5 track id: jatr-1076-21 rev. 1.3 5. pin assignments 5.1. rtl8212 dhs-qfp-128 package figure 4. pin assignments (rtl8212 dhs-qfp-128) 5.2. package identification (rtl8212 dhs-qfp-128) green package is indicated by a ?g? in the location marked ?t? in figure 4. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 6 track id: jatr-1076-21 rev. 1.3 5.3. rtl8212n qfn-76 package 1 11 9 8 7 6 5 4 3 2 10 12 19 18 17 16 15 14 13 p1 mdi ap avdd18 p0mdi dn p0mdicn p0mdibp p0 mdi cp p1 mdi an p1 mdi dp p1mdi dn p1mdi cn avdd18 p1 mdi bp p1 mdibn p0 mdi dp p0 mdi bn p0 mdi ap p0mdi an p1mdi cp avdd18 20 30 28 27 26 25 24 23 22 21 29 31 38 37 36 35 34 33 32 rvdd 33 resetb avdd1 2 avdd33 mdire f rtt2 vdd1 2 vdd1 2 p1 mode [ 1 ] p1 mode[2 ] p1 mode[ 0 ] vddio n c vddio avddpll avdd1 8 p1 mode rtt1 58 68 66 65 64 63 62 61 60 59 67 69 76 75 74 73 72 71 70 vddio dis_ autoxove r md c avdd18 avdd33 ledck ledda mdio phyadr [1 ] 39 49 47 46 45 44 43 42 41 40 48 50 57 56 55 54 53 52 51 svdd12 stxn clkin srxn srxp vddio vdd12 phyadr[3] phyadr[4] vdd12 stxp vdd12 vdd12 nc phyadr[2] svdd18 nc svss12 svss18 vddio lllllll txxxv rtl8212 n [ 3 ] avdd33 vdd1 2 vddio p0 mode [ 1 ] p0 mode[2 ] p0 mode[ 0 ] p0 mode [ 3 ] n c rvdd 33 vdd1 2 figure 5. pin assignments (rtl8212n qfn-76) 5.4. package identification (rtl8212n qfn-76) green package is indicated by a ?g? in the location marked ?t? in figure 5. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 7 track id: jatr-1076-21 rev. 1.3 5.5. rtl8211n qfn-76 package 1 11 9 8 7 6 5 4 3 2 10 12 19 18 17 16 15 14 13 avdd18 p0mdi dn p0mdi cn p0mdibp p0 mdi cp avdd18 nc p0 mdi dp p0 mdibn p0 mdiap p0 mdi an avdd18 39 49 47 46 45 44 43 42 41 40 48 50 57 56 55 54 53 52 51 svdd12 stxn clkin srxn srxp vddio vdd12 phyadr[3] phyadr[4] vdd12 stxp vdd12 vdd12 nc phyadr[2] svdd18 svss12 svss18 vddio nc nc nc nc nc nc nc figure 6. pin assignments (rtl8211n qfn-76) 5.6. package identification (rtl8211n qfn-76) green package is indicated by a ?g? in the location marked ?t? in figure 6. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 8 track id: jatr-1076-21 rev. 1.3 6. pin descriptions table 1. pin type abbreviations pin type definition i input o output i/o bi-directional b bias pu internal pull-up (typical value = 63k) pd internal pull-down (typical value = 51k) pwr power gnd ground note: the rtl8212/rtl8212n/rtl8211n is a dual-port/ single gigabit ethernet transceiver. each port, defined as port0 and port1 (port 0 for rtl8211n), is independent of the other, and is identical in performance and functionality. in this document, these pins for each port are spec ified by the port number, pin name, and signal number, respectively. for example, gmii transmit data pin 7 for port0 is shown as: p0txd7 6.1. media dependent interface pins table 2. media dependent interface pins qfn76 pin# dhs-qfp128 pin# pin name type description 1, 2 3, 4 6, 7 8, 9 11, 12 13, 14 16, 17 18, 19 7, 8 10, 11 13, 14 16, 17 20, 21 23, 24 26, 27 29, 30 p0mdiap/n p0mdibp/n p0mdicp/n p0mdidp/n p1mdiap/n p1mdibp/n p1mdicp/n p1mdidp/n i/o media dependent interface a~d. for 1000base-t operation, differential data from the media is transmitted and received on all four pairs. for 100base-tx and 10base-t operation, only mdiap/n and mdibp/n are used. auto mdix can reverse the pairs mdiap/n and mdibp/n. each of the differential pairs has an internal 100ohm termination resister. pins 11, 12, 13, 14, 16, 17, 18, and 19 of the qfn-76 package are n.c pins for the rtl8211n-gr. thertl8211n-gr is available in a qfn-76 package only. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 9 track id: jatr-1076-21 rev. 1.3 6.2. mii/gmii transmit interface pins table 3. mii/gmii transmit interface pins qfn76 pin# dhs-qfp128 pin# pin name type description - 117 69 p0gtxc p1gtxc i gmii transmit clock. 125mhz input clock. all transmit inputs must be synchronized to this clock during 1000base-t operation. this clock can be stopped in 10/100base-t modes, and also during auto-negotiation. - 116 68 p0txc p1txc o (12ma) mii transmit clock. all transmit inputs must be synchronized to this clock during 10/100 operation. it provides a 25mhz clock reference in 100base-tx mode, and 2.5mhz clock reference in 10base-t. the 25mhz clock is the default rate. - 118 70 p0txen p1txen i mii/gmii transmit enable. the synchronous input indicates that valid data is being driven on the txd bus. as the rtl8212 does not support 1000base-t half-duplex mode, the carrier-extension symbol is not transmitted onto the cable. txen is synchronous to gtxc in 1000base-t mode and synchronous to txc in 10/100base-tx mode. - 127 126 125 124 123 122 121 120 91 80 79 78 76 75 73 72 p0txd7 p0txd6 p0txd5 p0txd4 p0txd3 p0txd2 p0txd1 p0txd0 p1txd7 p1txd6 p1txd5 p1txd4 p1txd3 p1txd2 p1txd1 p1txd0 i pd mii/gmii transmit data bus. the width of this synchronous input bus varies with the speed mode: 1000: txd[7:0] are used. 10/100: txd[3:0] are used; txd[7:4] are ignored. txd[7:0] is synchronous to gtxc in 1000base-t mode and synchronous to txc in 10/100base-tx mode. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 10 track id: jatr-1076-21 rev. 1.3 6.3. mii/gmii receive interface pins table 4. mii/gmii receive interface pins qfn76 pin# dhs-qfp128 pin# pin name type description - 109 62 p0rxc p1rxc o pd (16ma) mii/gmii receive clock. the m ii/gmii receive output clock is used to synchronize receive d signals. its frequency depends upon the link speed: 1000: 125mhz 100: 25mhz 10: 2.5mhz - 107 60 p0rxdv p1rxdv o pd (16ma) mii/gmii receive data valid. this synchronous output is asserted when valid data is driven on rxd. rxdv is synchronous to rxc. - 115 65 p0crs p1crs o pd (12ma) mii/gmii carrier sense. this asynchronous output is asserted when a non-idle condition is detected at the twisted-pair interface, and de-asserted when idle or a valid end of stream delimiter is detected. in 10/100base-t half duplex, crs is also asserted during transmission. crs is asynchronous to txc and rxc. - 114 64 p0col p1col o pd (12ma) mii/gmii collision. this asynchronous output is asserted when a collision is detected in half-duplex modes. in full duplex mode, this out is forced low. col is asynchronous to txc, and rxc. - 110 63 p0rxer p1rxer o pd (12ma) mii/gmii receive error. when rxer and rxdv are both asserted, the symbol indicates an error symbol is detected on the cable. since the rtl8212 does not support 1000base-t half-duplex mode, carrier-extensi on receive symbol (rxer is asserted with rxdv deasserted) is not valid. rxdv is synchronous to rxc. 93 94 96 97 p0rxd7 p0rxd6 p0rxd5 p0rxd4 o pd (12ma) 98 101 102 106 p0rxd3 p0rxd2 p0rxd1 p0rxd0 o pd (16ma) - 48 49 51 52 p1rxd7 p1rxd6 p1rxd5 p1rxd4 o pd (12ma) mii/gmii receive data bus. the width of this synchronous output bus varies with the speed mode: 1000: rxd[7:0] are used. 10/100: rxd[3:0] are used; rxd[7:4] are ignored. rxd[7:0] is synchronous to rxc. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 11 track id: jatr-1076-21 rev. 1.3 qfn76 pin# dhs-qfp128 pin# pin name type description 54 55 56 59 p1rxd3 p1rxd2 p1rxd1 p1rxd0 o pd (16ma) 6.4. rgmii transmit interface pins table 5. rgmii transmit interface pins qfn76 pin# dhs-qfp128 pin# pin name type description - 117 69 p0gtxc p1gtxc i rgmii transmit clock. all transmit inputs must be synchronized to this clock. its frequency, with 50ppm tolerance, depends upon the link speed: 1000: 125mhz 100: 25mhz 10: 2.5mhz - 123 122 121 120 76 75 73 72 p0txd3 p0txd2 p0txd1 p0txd0 p1txd3 p1txd2 p1txd1 p1txd0 i pd rgmii transmit data bus. in rgmii 1000base-t mode, txd[3..0] runs at a double data rate with bits[3..0] presented on the rising edge of the gtxc, and bits[7..4] presented on the falling edge of the gtxc. txd[7..4] are ignored in this mode. in rgmii 10/100base-t modes, the transmitted data nibble is presented on txd[3..0] on the rising edge of gtxc and duplicated on the falling edge of gtxc. - 118 70 p0txen/ p0txctl p1txen/ p1txctl i pd rgmii transmit control. in rgmii mode, txen is used as txctl. txen is presented on the rising edge of gtxc. a logical derivative of txen and txer is presented on the falling edge of gtxc. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 12 track id: jatr-1076-21 rev. 1.3 6.5. rgmii receive interface pins table 6. rgmii receive interface pins qfn76 pin# dhs-qfp128 pin# pin name type description - 109 62 p0rxc p1rxc o (16ma) rgmii receive clock. all rgmii receive outputs must be synchronized to this clock. its frequency, with 50ppm tolerance, depends upon the link speed: 1000: 125mhz 100: 25mhz 10: 2.5mhz - 98 101 102 106 54 55 56 59 p0rxd3 p0rxd2 p0rxd1 p0rxd0 p1rxd3 p1rxd2 p1rxd1 p1rxd0 o pd (16ma) rgmii receive data bus. in rgmii 1000base-t mode, rxd[3..0] runs at a double data ra te with bits[3..0] presented on the rising edge of the rxc and bits[7..4] presented on the falling edge of the rxc. rxd[7..4] are ignored in this mode. in rgmii 10/100base_t modes, the received data nibble is presented on rxd[3..0] on the rising edge of rxc and duplicated on the falling edge of rxc. - 107 60 p0rxdv/ p0rxctl p1rxdv/ p1rxctl o pd (16ma) rgmii receive control. in rgmii mode, rxdv is used as rxctl. rxdv is presented on the rising edge of rxc. a logical derivative of rxdv and rxer is presented on the falling edge of rxc. 6.6. rsgmii interface pins table 7. rsgmii interface pins qfn76 pin# dhs-qfp128 pin# pin name type description 44 45 - srxp srxn o rsgmii receive pair. 2.5ghz differential serial output. the differential pair has an internal 100ohm termination resister. 49 50 - stxp stxn i rsgmii transmit pair. 2.5ghz differential serial input. the differential pair has an internal 100ohm termination resister. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 13 track id: jatr-1076-21 rev. 1.3 6.7. serial management interface pins table 8. serial management interface pins qfn76 pin# dhs-qfp128 pin# pin name type description 71 1 mdc i management data clock. the clock reference for the serial management interface. 70 128 mdio i/o pu (8ma) management data input/output. mdio transfer management data; in and out of the device synchronous to the rising edge of mdc. 54 55 96 97 phyadr[4]/ p0rxd5 phyadr[3]/ p0rxd4 o pd (12ma) 56 58 98 101 phyadr[2]/ p0rxd3 phyadr[1]/ p0rxd2 o pd (16ma) phy address select. these pins ar e the four uppermost bits of the 5-bit ieee-specified phy addr ess. the states of these four pins are latched during power-up or reset. the lowest bit of the 5-bit phy address is hard-wired to each of the dual ports within the device. ?0? represents port0, and ?1? represents port1. 6.8. serial led interface pins table 9. serial led interface pins qfn76 pin# dhs-qfp128 pin# pin name type description 72 2 ledck o (8ma) serial led clock. reference output clock for serial led interface. the 12.5mhz clock outputs periodically. data is latched on the rising edge of ledck. 73 3 ledda o (8ma) serial led data output. serial bit stream of link status information. 32 52 ledmode/ p1rxd4 o pd (12ma) serial led mode select. these pi ns are used to configure led operation mode. the state of this pin is latched during power-up or reset. there are two led display modes: 0: mode 0 1: mode 1 www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 14 track id: jatr-1076-21 rev. 1.3 6.9. system clock interface pins table 10. system clock interface pins qfn76 pin# dhs-qfp128 pin# pin name type description - 42 xtal1 i phy reference clock input. 25mhz 50ppm tolerance crystal reference or oscillator input. when using a crystal, connect a loading capacitor from each pad to ground. when clkin is used, this pin is not valid and should be pulled-low. the maximum xtal1 input voltage is 1.8 v. - 41 xtal2 o phy reference clock output. 25mhz 50ppm tolerance crystal reference or oscillator output. when clkin is used, this pin is not valid and should be floating. 47 85 clkin i 25mhz clock input. 25mhz 50ppm tolerance clock input. when rsgmii is used, this pin is able to accept a 25mhz clock signal generated from the mac device (rtl8212n/rtl8211n only). note: this pin should be tied to ground for rtl8212 dhs-qfp128 applications. the maximum clkin input voltage is 1.8v. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 15 track id: jatr-1076-21 rev. 1.3 6.10. configuration and control pins table 11. configuration and control pins qfn76 pin# dhs-qfp128 pin# pin name type description - - 93 94 intf_sel[1] intf_sel[0] o pd (12ma) mac interface mode select. intf_sel[1:0] determines the mac interface configuration for both port0 and port1: 00: rsgmii (default mode) 01: gmii 10: rgmii 11: reserved 63 107 p0mode[3] o pd (16ma) 64 67 68 110 114 115 p0mode[2] p0mode[1] p0mode[0] o pd (12ma) 35 60 p1mode[3] o pd (16ma) 36 37 38 63 64 65 p1mode[2] p1mode[1] p1mode[0] o pd (12ma) auto-negotiation configuration. pxmode[3:0] presets each port?s advertise link ability (speed, duplex, and master/slave). the states of this pin is latched during power-up or reset. pxmode[3:0] defined as: 0000: auto-negotiation, adver tise all capabilities, prefer master 0001: auto-negotiation, advertis e all capabilities, prefer slave 0010: auto-negotiation, advertise only 100base-tx half duplex 0011: auto-negotiation, advertise only 100base-tx full duplex 0100: reserved 0101: reserved 0110: reserved 0111: reserved 1000: auto-negotiation, advertise only 1000base-t full duplex, force master 1001: auto-negotiation, advertise only 1000base-t full duplex, force slave 1010: auto-negotiation, advertise only 1000base-t full duplex, prefer master 1011: auto-negotiation, advertise only 1000base-t full duplex, prefer slave 1100: auto-negotiation, advertise all capabilities, force master 1101: auto-negotiation, advertise all capabilities, force slave 1110: auto-negotiation, advertise only 10base-t half duplex 1111: auto-negotiation, advertise only 10base-t full duplex - 54 txdly o pd gtxc clock delay select. this pin enables gtxc input delay in rgmii mode (see table 22, page 27 for detailed configuration). - 55 rxdly o pd rxc clock delay select. this pin enables rxc output delay in rgmii mode (see table 22, page 27 for detailed configuration). 62 106 dis_ autoxover o pd 1: disable auto crossover detection 0: enable auto crossover detection www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 16 track id: jatr-1076-21 rev. 1.3 6.11. miscellaneous pins table 12. miscellaneous pins qfn76 pin# q128 pin# pin name type description 29 45 resetb i hardware reset. active low reset signal. to complete the reset function, this pin must be asserted for at least 10ms. it must be pulled high for normal operation. 23 35 mdi_ref i b mdi bias resistor. adjusts the reference current for both phys. a resistor of 2.49k ? 1% is connected between this pin and ground. 24 37 rtt1 o test pin 1. reserved pin for internal analog debugging. connect to ground through a 1k ? resistor. if debug is not important and there are board space constraints, this pin can be left floating. 25 38 rtt2 i test pin 2. reserved pin for internal analog debugging. connect to ground through a 1k ? resistor. if debug is not important and there are board space constraints, this pin can be left floating. - 5 atest o analog test pin. reserved pin for internal analog debugging. connect to ground through a 1k ? resistor. if debug is not important and there are board space constraints, this pin can be left floating. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 17 track id: jatr-1076-21 rev. 1.3 6.12. power and ground pins table 13. power and ground pins qfn76 pin# dhs-qfp128 pin# pin name type description 3.3v power supply 21, 26, 74 4, 19 32, 39 avdd33 pwr analog power 3.3v. 30, 66 46, 113 rvdd33 pwr analog power 3.3v for internal regulator. 1.8v power supply 5, 10, 15, 20 6, 12 18, 25, 31 avdd18 pwr analog power 1.8v. 22 33 avddpll pwr analog power 1.8v for pll this pin is filtered with a low resistance series ferrite bead and 1000pf + 2.2uf shunt capacitors to ground. 43 81 svdd18 pwr analog power 1.8v for rsgmii. 1.2v power supply 27 40 avdd12 pwr analog power 1.2v. 51 89 svdd12 pwr analog power 1.2v for rsgmii. 31, 34, 39, 42, 53, 57, 61, 65 50, 58, 66, 74, 92, 99, 105, 111 vdd12 pwr digital power 1.2v for digital core. 2.5v power output pin 28, 33, 41, 52, 60, 69 44, 57, 71, 90, 103, 119 vddio pwr digital i/o power 2.5v. this power is generated from an internal regulator. connect the following group of pins together dhs-qfp-128: group (44, 57, 71), group (90, 103, 119) qfn-76: group (28, 33, 41), group (52, 60, 69) if mii/gmii/rgmii is not used, no external pcb trace is required. only connect to ground through a decoupling capacitor. ground gnd pad 9, 15, 22, 28, 36, 43, avss gnd analog ground. gnd pad 34 avsspll gnd pll ground. gnd pad 53, 61, 67, 77, 95, 100, 108, 112 vss12 gnd digital core ground. gnd pad 47, 104 vssio gnd digital i/o ground. 46 84 svss18 pwr analog 1.8v gnd for rsgmii. 48 86 svss12 pwr analog 1.2v gnd for rsgmii. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 18 track id: jatr-1076-21 rev. 1.3 7. functional description 7.1. mdi interface the rtl8212/rtl8212n/8211n uses a single common mdi interface to support 10base-t, 100base-tx, and 1000base-t. this interface consists of four signal pairs-a, b, c, and d. each signal pair consists of two bi-directional pins that can tr ansmit and receive at the same tim e. the mdi interface has internal termination resistors, and theref ore reduces bom cost and pcb comp lexity. for 1000base-t, all four pairs are used in both directions at the same time. for 10/100 links and during auto-negotiation, only pairs a and b are used. table 14 shows the mapping between the pairs and the rj-45 signals. table 14. mapping of twisted-pair outputs to rj-45 connectors pairs rj-45 connector a 1 and 2 b 3 and 6 c 4 and 5 d 7 and 8 7.1.1. crossover detection and auto correction the rtl8212/rtl8212n/8211n automatically determines whether or not it needs to crossover between pairs; removing the need for an external crossover cable. when connecting to a device that does not perform mdi crossover, the rtl8212/rtl8212n/rtl82 11n automatically switch es its pin pairs to communicate with the connecting device. when connec ting to a device that do es have mdi crossover capability, an algorithm determines whic h end performs the crossover function. the crossover detection and au to correction function can be disabled by strap pin. the rtl8212/rtl8212n/8211n is set to mdi crossover by default. the pin mapping in mdi and mdi crossover mode is given in table 15. table 15. media dependent interface pin mapping mdi mdi crossover pairs 1000base-t 100base-tx 10base-t 1000base-t 100base-tx 10base-t a a tx tx b rx rx b b rx rx a tx tx c c unused unused d unused unused d d unused unused c unused unused www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 19 track id: jatr-1076-21 rev. 1.3 7.1.2. polarity correction the rtl8212/rtl8212n/8211n automatically correct pol arity errors on the rece iver pairs in 10base-t and 1000base-t modes. in 100base-tx m ode, the polarity is irrelevant. in 1000base-t mode, receive polarity errors are auto matically corrected based on the sequence of idle symbols. once the descrambler is locked the polarity is also locked on all pa irs. the polarity becomes unlocked only when the receiver loses lock. in 10base-t mode, polarity errors are corrected base d on the detection of valid spaced link pulses. the detection begins during the mdi cr ossover detection phase and locks when the 10base-t link is up. the polarity becomes unlocked when the link is down. figure 7. conceptual example of polarity correction www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 20 track id: jatr-1076-21 rev. 1.3 7.1.3. mac interface the rtl8212/rtl8212n/rtl8211n mac interface supports mii/gm ii, rgmii, and rsgmii (2.5gbps serial interface; rtl 8212n and rtl8211n only). the mac in terface selection is set by intf_sel[1..0]. table 16 shows th e data rates supported through each interface, and table 17 shows each mac interface operation mode. table 16. data rates supported through each interface mac interface 10base-t 100base-tx 1000base-t mii - gmii - - rgmii rsgmii (rtl8212n/rtl8211n only) table 17. mac interface modes of operation mac interface speed data width clock frequency clock edge notes 100 4 bits 25mhz rising - mii 10 4 bits 2.5mhz rising - gmii 1000 8 bits 125mhz rising - 1000 4 bits 125mhz rising/falling - 100 4 bits 25mhz rising 1 rgmii 10 4 bits 2.5mhz rising 1 1000 1 bits 125mhz rising 2 100 1 bits 125mhz rising 3 rsgmii (rtl8212n/rtl8211n only) 10 1 bits 125mhz rising 3 note 1: the data may be duplicated on the falling edge of the appropriate clock when the interface operates at 10 and 100mbps speeds. note 2: the internal pll generates 20 sub-phase clock signals by dividing the 125mhz clock. the data can be latched on the rising edge of each sub-phase signal. the data bandwidth of the rsgmii interface is up to 2.5gbps (125m*20*1). note 3: operation at 10 and 100mbps uses respectively only 1% and 10% of the rsgmii interface bandwidth. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 21 track id: jatr-1076-21 rev. 1.3 7.2. gigabit media independent interface (mii/gmii) table 18 indicates the signal mapping of the rtl 8212 to the gigabit media independent interface (mii/gmii). mii signaling to support 100base-tx a nd 10base-t modes is implemented by sharing pins of the gmii interface. the interface supports gmii to copper connections at all three speeds. the gmii mode does not support carrier extens ion and packet concatenation in both the transmit and the receive directions, due to not having a txer pin. table 18. gigabit media independent interface rtl8212 pins mii gmii gtxc - gtx_clk txc txc - txen tx_en tx_en txd[7..4] - txd[7..4] txd[3..0] txd[3..0] txd[3..0] rxc rx_clk rx_clk rxer rx_er rx_er rxdv rx_dv rx_dv rxd[7..4] - rxd[7..4] rxd[3..0] rxd[3. .0] rxd[3..0] crs crs crs col col col figure 8. gmii signal diagram www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 22 track id: jatr-1076-21 rev. 1.3 in 1000base-t operation, when gmii mode is selecte d, a 125mhz transmit clock is expected on gtxc, and rxc sources the 125mhz receive clock. at th e same time, txc sources 25mhz, 2.5mhz, or 0mhz depending on the mdi status. in 10base-t and 100base-tx modes, when mii mode is selected, bo th txc and rxc source 25mhz or 2.5mhz, respectively. txd[3:0] and rxd[3:0] signals are used. gtxc and txd[7..4] signals must be pulled high or low and must not be left floating. rxd[7..4] are driven low. figure 9. mii signal diagram during the transition from one speed to another, a dead time of 1.5 clock cycl es may occur in rxc and txc (in order to ensure a glitch-free clock). note: the mii and gmii interfaces are enabled by hardw are configuration bits intf_sel[1..0] that are latched at the end of hardware reset. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 23 track id: jatr-1076-21 rev. 1.3 7.2.1. reduced gmii (rgmii) the rtl8212 supports the rgmii rev. 1.3 specification. this interface reduces the interconnection between the mac and the phy to 12 pi ns. in order to accomp lish this objective, the data paths and all associated control signals are reduced. control signa ls are multiplexed and both edges of the clock are used. for gigabit operation, the transmit a nd the receive clocks operate at 125mhz. for 10/100 operation, the clocks operate at 2.5mhz or 25mhz respectively. once the rgmii is selected in all three speeds, transmit control is presented on both clock edges of gtxc (txc). receive control (rx_ctl) is presented on both clock edges of rxc (rxc). the rgmii interface is selected by setting intf_sel[1..0] to ?10?. table 19. mac interface modes of operation rtl8212 pins rgmii description gtxc txc 125mh, 25mhz, or 2.5mhz transmit clock, with 50ppm tolerance, based on the selected speed. txen tx_ctl transmit control signals. tx_en is encoded on the rising edge of gtxc. tx_er xor tx_en is encoded on the falling edge of gtxc. txd[3..0] td[3..0] transmit data. in 1000base-t mode, bits 3:0 are presented on the rising edge of gtxc, and bits 7:4 is presented on the falling edge of gtxc. in 10/100 mode, bits 3:0 is presented on the rising edge of gtxc, and duplicated on the falling edge of gtxc. rxc rxc 125mh, 25mhz, or 2.5mhz receive clock, with 50ppm tolerance, based on the selected speed. rxdv rx_ctl receive control signals. rx _dv is encoded on the rising edge of rxc, rx_er xor rx_dv is encoded on the falling edge of rxc. rxd[3..0] rd[3..0] receive data. in 1000base-t mode, bits 3: 0 is presented on the rising edge of rxc, and bits 7:4 are presented on the falling edge of rxc. in 10/100 mode, bits 3:0 is presented on the rising edge of rxc, and duplicated on the falling edge of rxc. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 24 track id: jatr-1076-21 rev. 1.3 figure 10. rgmii signal diagram 7.2.2. 10/100mbps functionality this interface can be used to implement the 10/100mbps ethernet media independent interface (mii) by reducing the clock rate to 25mhz for 100mbps ope ration and 2.5mhz for 10mbps. the txc will always be generated by the mac and rxc will always be ge nerated by the phy. during packet reception, the rxc may be stretched on either the positive or negative pulse to accommodate the transition from the free running clock to a data-synch ronous clock domain. when the spee d of the phy changes, a similar stretching of the positive or negative pulses is allowed. no glitch of the clocks is allowed during speed transitions. the interface will operate at 10 an d 100mbps speeds exactly the same wa y it does at gigabit speed with the exception that the data may be duplicated on the falling e dge of the appropriate clock. the mac must hold txen (tx_ctl) low until th e mac has ensured that txen (tx_ctl) is operating at the same speed as the phy. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 25 track id: jatr-1076-21 rev. 1.3 7.2.3. tx_ctl and rx_ctl coding to reduce power consumption of th is interface, tx_er and rx_er are encoded in a manner that minimizes transitions during normal network operati on. this is done via the fo llowing encoding method. note that the rtl8212 does not support half-duplex in 1000base-t and the gmii_tx_er signal is tied to logic low at all times. carrier extend and tr ansmit errors never appear at the transmitting and receiving end. tx_ctl gmii_tx_er (xor) gmii_tx_en rx_ctl gmii_rx_er (xor) gmii_rx_dv while receiving a valid frame with no errors, rx_dv=tr ue is generated as a logic high on the rising edge of rxc, and rx_er=false is generated as a logic high on the falling edge of rxc. when no frame is being received, rx_dv=false is generated as a logic low on the rising edge of rxc, and rx_er=false is generated as a logic low on the falling edge of rxc. when receiving a valid frame with errors, rx_dv=true is generated as a logic high on the rising edge of rxc, and rx_er=true is generated as a logic low on the falling edge of rxc. during normal frame transmission, the signal stays at high for both edges of txc. during normal inter-frame, the signal st ays low for both edges. table 20. tx_er and tx_en encoding tx_ctl gmii_tx_en gmii_tx_er description 0, 0 0 0 normal inter-frame 1, 1 1 0 normal data transmission note: as gmii_tx_er is always tied to logic low in the rt l8212, no transmit error symbol or carrier extend symbol occurs in data transmission. figure 11. rgmii data transmission www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 26 track id: jatr-1076-21 rev. 1.3 table 21. rx_er and rx_dv encoding rx_ctl gmii_rx_dv gmii_rx_er description 0, 0 0 0 normal inter-frame 0, 1 0 1 carrier sense 1, 1 1 0 normal data reception 1, 0 1 1 data reception error note 1: the mac is designed to acquire the link status, speed and duplex mode of the phy via mdc/mdio polling, so the rtl821 does not implement specific code onto rxd[3.. 0] to inform mac of the phy status during normal inter-frame. note 2: in addition to the encoding of rx_dv and rx_er as indicated in table 21, a value of ?ff? also exists on the rxd[7..0] simultaneously when th e carrier sense symbol occurs. figure 12. rgmii data reception without error figure 13. rgmii data reception with error www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 27 track id: jatr-1076-21 rev. 1.3 7.2.4. in-band status crs is indicated where: ? rx_dv is true ? where rx_dv is false, rx_er is true, and a value of ?ff? exists on the rxd[7..0] bits simultaneously carrier extend and carrier extend error are not suppor ted by the rtl8212. collision is determined at the mac by the assertion of txen being true while eith er crs or rxdv are true. the phy will not assert crs as a result of txen being true. 7.2.5. four rgmii modes the rtl8212 supports four different timing modes of operation. hard ware strapping pins txdly and rxdly can be used to select between the four rgmii timing modes. refer to table 44, page 49, for rgmii mode timing. each bit adjusts the delay of data with respect to clock edges. for both inputs and outputs of the phy the data can change either simultaneously with the clock edges, or the data can ha ve setup and hold with respect to clock edges. table 22. rgmii timing modes mode txdly rxdly phy input gtxc vs. data phy output rxc vs. data mode 0 0 0 meet setup and hold time simultaneous with clock edge mode 1 0 1 meet setup and hold time meet setup and hold time mode 2 1 0 simultaneous with clock edge simultaneous with clock edge mode 3 1 1 simultaneous with clock edge meet setup and hold time www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 28 track id: jatr-1076-21 rev. 1.3 7.3. reduced serial gmii (rtl8212n and rtl8211n only) to reduce pcb complexity and ic pin count, realtek offers a proprietary inte rface; the realtek reduced serial gigabit media independent interface (rsgmii). this innovative 2.5gbps serial interface provides an up to 5 inch long mac to phy communication pa th. the rsgmii can carry the full duplex gigabit ethernet data streams of two ports simultaneously, a nd recover clock from the data rather than use a dedicated clock. the rsgmii reduces the interconnection between the gigabit ethernet phy and mac to only 4 pins. figure 14 depict s the rsgmii interconnection. port0 port1 rsgmii tx rx mac port0 port1 rsgmii tx rx phy figure 14. rsgmii interconnection diagram the rsgmii interface runs at 2.5 gbps in 10/100/1000mbps modes. cl early, a 2.5gbps data rate is excessive for interfaces operating at 10/100mbps. wh en operating in these conditions, the interface elongates each byte of data by 10 times for 100m bps, and by 100 times for 10mbps, through a rate adaptation block. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 29 track id: jatr-1076-21 rev. 1.3 the data paths and all associated control signals are transmitted from each port and recovered at the receiver side via proprietary transmission en code/decode and serial/d e-serial translation. taking the realtek rtl8369 and rtl 8212n as examples (see figure 15), the rtl8369 contains four rsgmii (4 pairs) and the rtl8212n contains one rs gmii (1 pair). the rtl8369 generates differential sntx, n=0~3 signals to four rtl 8212n?s, and receives differential snrx, n=0~3 signals from four rtl8212n?s. each rsgmii carries two gigabits of ethernet data from phy to mac and mac to phy. in traditional gmii applications, the mac to phy in terface requires at least 20 pins to carry 1 port?s bi-directional gigabit ethernet tr affic. a mac to phy rsgmii needs only 4 pins to carry two port?s gigabit ethernet traffic. this gr eatly improves pcb layout size and comp lexity in gigabit switch design. figure 15. realtek 8g switch application with rsgmii www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 30 track id: jatr-1076-21 rev. 1.3 7.3.1. rsgmii data transfer at the receive side, gmii signals of the two gi gabit ethernet phy ports enter at 10/100/1000mbps, clocked at 2.5/25/125mhz. each port passes these si gnals through ethernet phy receive rate adaptation to output data rxd[7..0] in the 125 mhz clock domain. both rxd are th en sent to the individual pcs transmit state machine to generate proprietary encoded code-words a and b . the phy combines the code-words a and b generated from the two ports to a code-word c , and converts it to a serial (bit by bit) stream for the ethernet mac at a 2.5gbps data rate. at the transmit side, the phy de-serializes data to recover th e encoded code-word c . next the synchronization block checks the code-word c to determine the synchronization status between links, and to realign if it detects a loss of synchronization. the ethernet phy separate s the synchronous code-word c, into a and b for each port. each port?s code-word is then recovered to the gmii signal in the 125mhz clock domain by passing through individual pcs receive state machines. both the d ecoded gmii signals have to pass the phy transmit rate adaptation block to output data segments according to the port speed. the transmitting and receiving operation flow on the ethe rnet mac side is the same as th e ethernet phy side. figure 16 and figure 17 show the functional block diagram at the p hy and mac side respectivel y. they illustrate how the pcs layer is modified and incorporated at th e phy and mac side within the rsgmii interface. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 31 track id: jatr-1076-21 rev. 1.3 port1 phy receive rate adaptation port1 pcs transmit state machine p0rx_dv p0rx_er p0rxd[7..0] p0rx_clk 125mhz p1rx_dv p1rx_er p1rxd[7..0] p1rx_clk 125mhz code-word a code-word b port0 serializer rx port1 port1 port0 pcs receive state machine p0tx_dv p0tx_er p0txd[7..0] p0tx_clk 125mhz p1tx_en p1tx_er p1txd[7..0] p1tx_clk 125mhz port0 tx code-word c phy transmit rate adaptation port0 port0 de- serializer synchro- nization p0tx_clk 2.5/25/125mhz gmii signals from port0 p1tx_clk 2.5/25/125mhz gmii signals from port1 p0rx_clk 2.5/25/125mhz gmii signals from port0 p1rx_clk 2.5/25/125mhz gmii signals from port1 code-word a code-word b code-word c figure 16. rsgmii functional block diagram at ethernet phy side figure 17. rsgmii functional block diagram at ethernet mac side www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 32 track id: jatr-1076-21 rev. 1.3 7.4. mdc/mdio management interface the rtl8212/rtl8212n/rtl8211n support the ieee compliant management data input/output (mdio) interface. this is the only method for the mac to acquire the phy statuses. the mii management interface registers are wr itten and read serially, using the mdc/mdio pins. data transferred to and from the mdio pins is synchronized with th e mdc clock. all transfers are initiated by the mac. a clock of up to 2.5mhz must drive th e mdc pin of the rtl8212/rtl8212n/rtl8211n. the mdio frame structure starts with a 32-bit preamble, whic h is required by the rtl8212/8211. following bits include a start-of-frame marker, an op- code, a 10-bit address field, and a 16-bit data field. the address field is divided into two 5-bit segments . the first segment identifies the phy address and the second identifies the re gister being accessed. the four uppermost bits of the 5-b it phy address are determined by th e hardware strappi ng values during power up. the lsb of the phy address is ?0? for po rt0 and ?1? for port1. the mdio protocol provides both read and write operations. du ring a write operation, the mac drives the mdio line for the entire frame. for a read operation, a turn-around time is inserted in the frame to allow the phy to drive back to the mac. the mdio pin of the mac must be put in a high-impedance during these bit times. figure 18 and figure 19, page 33 depict the mdio r ead and write frame format respectively. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 33 track id: jatr-1076-21 rev. 1.3 7.4.1. preamble suppression the rtl8212/rtl8212n/rtl8211n is permanently programmed for preamble suppression. a preamble of 32 bits is requi red only for the first read or write. th e management preamble may be as short as 1 bit. figure 18. mdio read frame format figure 19. mdio write frame format www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 34 track id: jatr-1076-21 rev. 1.3 7.5. hardware configuration interface the rtl8212/rtl8212n is a dual-port device. the r tl8211n is a single-port device. configuration options such as mac interface, physical address, phy operating mode are configured by using the configuration pins. these pins are shared with gmii/rgmii rece ive pins. except for the phy operating mode, both ports may be configured independently . settings are implemented simultaneously after power-on reset. table 23 shows the configuration definitions. table 23. configuration pin definitions configuration description intf_sel[1:0] interface select: intf_sel[1:0] specifies the mac interface oper ating mode for both ports. 00: rsgmii 01: mii/gmii 10: rgmii 11: reserved phyadr[4:1] phy address: phyadr[4:1] sets the uppermost 4 bits of the 5-bit phy address upon reset. the lsb is ?0? for port 0 and ?1?for port1. ledmode serial led mode select: ledmode specifies the serial led display mode for both ports. there are two led display modes in the rtl8212/8211. 0: mode 0 1: mode 1 gtxclk gtxclk clock delay select: gtxclk determin es the gtxclk input delay in rgmii mode. 0: output data may change simultaneously with the gtxclk edges 1: output data can have setup time and hold time with respect to gtxclk edges rxclk rxclk clock delay select: rxclk determines the rxclk output delay in rgmii mode. 0: output data may change simultaneously with the rxclk edges 1: output data can have setup time and hold time with respect to rxclk edges www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 35 track id: jatr-1076-21 rev. 1.3 7.6. led configuration the rtl8212/rtl8212n/rtl8211n supports serial led status streams for led display. the forms of led status streams are controlled by ledmode pins (see table 24) which are latched upon reset. all led statuses are represented as active-low. table 24. led mode led mode output sequences 0 dup/col, link/act, spd1000, spd100 1 dup/col, spd1000/act, (spd100,spd10)/act table 25. led status led status description col/fulldup collision, full duplex indicator. blinks every 43ms when collision occurs. low for full duplex, and high for half duplex mode. link/act link, activity indicator. low for link established. blinks every 43ms when the corresponding port is transmitting or receiving. spd1000 1000mbps speed indicator. low for 1000mbps. spd1000/act 1000mbps speed/activity indicator. low for 1000mbps. blinks every 43ms when the corresponding port is tr ansmitting or receiving. (spd100,spd10)/act 10/100mbps, speed/activity indicator. low for 10/100mbps. blinks every 43ms when the corresponding port is tr ansmitting or receiving. 7.6.1. led system application examples ? 4 single-color leds: link/act, spd1000, spd100, dup/col (set ledmode=0) ? 3 single-color leds: link/act, spd1000, spd100 (set ledmode=0) ? 2 single-color, 1 bi-color leds: link/act, dup/col, spd1000/spd100 (set ledmode=0) ? 1 single-color, 1 bi-color led: dup/ col, spd100/spd10/100/act (set ledmode=1) www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 36 track id: jatr-1076-21 rev. 1.3 7.6.2. serial stream order every bit stream is output port by port, from port0 to port1 with col/fulldup as the first bit in a port stream. table 26. serial stream order (mode 0) clock 0 1 2 3 4 5 6 7 mode 0 port 0 dup/col port 0 link/act port 0 spd1000 port 0 spd100 port 1 dup/col port 1 link/act port 1 spd1000 port 1 spd100 74164 pin h g f e d c b a table 27. serial stream order (mode 1) clock - - 0 1 2 3 4 5 mode 1 - - port 0 dup/col port 0 spd1000/act port 0 spd100/act port 1 dup/col port 1 spd1000/act port 1 spd100/act 74164 pin h g f e d c b a 7.7. system clock interface figure 20. clock generated from mac (rsgmii mode) note: when clkin is used, pull the x1 pin low to gnd. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 37 track id: jatr-1076-21 rev. 1.3 7.8. register descriptions the first six registers of the mi i are defined by the mii specificatio n. other registers are defined by realtek semiconductor corp. for in ternal use and are reserved. 7.8.1. register symbols ro: rw: ll: read only read/write latch low until cleared lh: sc: latch high until cleared self clearing 7.8.2. mii specification defined registers table 28. mii specification defined registers register description default 0 control register. 0x1140 1 status register. 0x7949 2 phy identifier 1 register. 0x001c 3 phy identifier 2 register. 0xc912 4 auto-negotiation advertisement register. 0x01e1 5 auto-negotiation link partner ability register. 0x0000 6 auto-negotiation expansion register. 0x0000 7 auto-negotiation page transmit register. 0x2001 8 auto-negotiation link partner next page register. 0x0000 9 1000base-t control register. 0x0f00 10 1000base-t status register. 0x0000 15 extended status. 0x3000 www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 38 track id: jatr-1076-21 rev. 1.3 7.8.3. register0: control table 29. register0: control bit (s) name description mode default 0.15 reset 1: phy reset 0: normal operation this bit is self-clearing. rw/sc 0 0.14 loopback this will loopback txd to rxd and ignore all activity on the cable media. 1: enable loopback 0: normal operation rw 0 0.13 speed selection[0] [0.6, 0.13] speed selection[1:0]. 11: reserved 10: 1000 mbps 01: 100 mbps 00: 10 mbps note: the smi: serial management interface, composed of mdc, mdio, allows the mac to manage the phy. rw 0 0.12 auto negotiation enable this bit can be set through smi (read/write). 1: enable auto-negotiation process 0: disable auto-negotiation process rw 1 0.11 power down 1: power down. all functions will be disabled except smi read/write function 0: normal operation rw 0 0.10 isolate 1: electrically isolates the phy from mii/gmii/rgmii/rsgmii. phy is still able to respond to mdc/mdio 0: normal operation rw 0 0.9 restart auto negotiation 1: restart auto-negotiation process 0: normal operation rw/sc 0 0.8 duplex mode 1: full duplex operation 0: half duplex operation when auto-negotiation is enabled, this bit reflects the result of auto-negotiation (read only). when auto-negotiation is disabled, this bit can be configured through smi (read/write). rw 1 0.7 collision test 1: collision test enabled 0: normal operation when set, this bit will cause the col signal to be asserted in response to the assertion of txen within 512-bit times. the col signal will be de-asserted within 4-bit times in response to the de-assertion of txen. ro 0 0.6 speed selection[1] see bit 13. rw 1 0.[5:0] reserved reserved. ro 0 www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 39 track id: jatr-1076-21 rev. 1.3 7.8.4. register1: status table 30. register1: status bit (s) name description mode default 1.15 100base-t4 0: no 100base-t4 capability the rtl8212/rtl8212n/rtl8211n does not support 100base-t4 mode. this bit should always be 0. ro 0 1.14 100base-x full duplex 1: 100base-x full duplex capable 0: not 100base-x full duplex capable ro 1 1.13 100base-x half duplex 1: 100base-x half duplex capable 0: not 100base-x half duplex capable ro 1 1.12 10mbps full duplex 1: 10mbps full duplex capable 0: not 10mbps full duplex capable ro 1 1.11 10mbps half duplex 1: 10mbps half duplex capable 0: not 10mbps half duplex capable ro 1 1.10 100base-t2 full duplex 0: no 100base-t2 full duplex capability. the rtl8212/rtl8212n/rtl8211n does not support 100base-t2 mode. this bit should always be 0. ro 0 1.9 100base-t2 half duplex 0: no 100base-t2 half duplex capability the rtl8212/rtl8212n/rtl8211n does not support 100base-t2 mode. this bit should always be 0. ro 0 1.8 extended status 1: extended status information in register 15 the rtl8212/rtl8212n/rtl8211n always supports extended status register. ro 1 1.7 reserved reserved. ro 0 1.6 mf preamble suppression the rtl8212/rtl8212n/rtl8211n will accept management frames with preamble suppressed. ro 1 1.5 auto-negotiate complete 1: auto-negotiation process completed. 0: auto-negotiation process not completed. ro 0 1.4 remote fault 1: remote fault indication from link partner has been detected. 0: no remote fault indication detected. this bit will remain set until it is cleared by reading register 1 via management interface. ro/lh 0 1.3 auto-negotiation ability 1: auto-negotiation capable (permanently=1) 0: without auto-negotiation capability. ro 1 1.2 link status 1: link has never failed since previous read 0: link has failed since previous read if link fails, this bit will be set to 0 until bit is read. ro/ll 0 1.1 jabber detect 1: jabber detected 0: no jabber detected jabber is supported only in 10base-t mode. ro/lh 0 1.0 extended capability 1: extended register capable. (permanently=1) 0: not extended register capable ro 1 www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 40 track id: jatr-1076-21 rev. 1.3 7.8.5. register2: phy identifier 1 register the phy identifier registers #1 and #2 together form a unique identifier for the phy section of this device. the identifier consists of a concatenation of the organizationally unique identifier (oui), the vendor's model number and the model revision number. a phy may return a value of zero in each of the 32 bits of the phy identifier if desired. the phy id entifier is intended to support network management. table 31. register2: phy identifier 1 register reg. bit name description mode default 2.[15:0] oui composed of the 3 rd to 18 th bits of the organizationally unique identifier (oui), respectively. ro 001c h 7.8.6. register3: phy identifier 2 register table 32. register3: phy identifier 2 register reg. bit name description mode default 3.[15:10] oui assigned to the 19 th through 24 th bits of the oui. ro 110010 3.[9:4] model number manufacturer?s model number. ro 010001 3.[3:0] revision number manufacturer?s revision number. ro 0010 www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 41 track id: jatr-1076-21 rev. 1.3 7.8.7. register4: auto-negotiation advertisement this register contains the advertisement abilities of this device as they will be transmitted to its link partner during auto-negotiation. table 33. register4: auto-negotiation advertisement reg. bit name description mode default 4.15 next page 1: additional next pages exchange desired 0: no additional next pages exchange desired rw 0 4.14 reserved permanently=0 ro 0 4.13 remote fault 1: set remote fault bit 0: do not set remote fault bit rw 0 4.12 reserved for future technology rw 0 4.11 asymmetric pause 1: advertises that the rtl8212/rtl8212n/rtl8211n has asymmetric flow control capability 0: no asymmetric flow control capability rw 0 4.10 pause 1: advertises that the rtl8212/rtl8212n/rtl8211n has flow control capability. 0: no flow control capability. rw 0 4.9 100base-t4 1: 100base-t4 capable 0: not 100base-t4 capable (permanently=0) ro 0 4.8 100base-tx-fd 1: 100base-tx full duplex capable 0: not 100base-tx full duplex capable rw 1 4.7 100base-tx 1: 100base-tx half duplex capable 0: not 100base-tx half duplex capable rw 1 4.6 10base-t-fd 1: 10base-tx full duplex capable 0: not 10base-tx full duplex capable rw 1 4.5 10base-t 1: 10base-tx half duplex capable 0: not 10base-tx half duplex capable rw 1 4.[4:0] selector field [00001]=ieee802.3 ro 00000 note 1: the setting of register 4 has no effect unless auto-negotiation is restarted or link down. note 2: if 1000base-t is advertised, then the re quired next pages are automatically transmitted. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 42 track id: jatr-1076-21 rev. 1.3 7.8.8. register5: auto-negotiation link partner ability this register contains the advertised abilities of the link partner as received during auto-negotiation. the content changes after a su ccessful auto-negotiation. table 34. register5: auto-neg otiation link partner ability reg. bit name description mode default 5.15 next page 1: link partner desires next page transfer 0: link partner does not desire next page transfer ro 0 5.14 acknowledge 1: link partner acknowledges reception of flp words 0: no acknowledgement by link partner ro 0 5.13 remote fault 1: remote fault indicated by link partner 0: no remote fault indicated by link partner ro 0 5.12 reserved reserved. ro 0 5.11 asymmetric pause 1: asymmetric flow control supported by link partner 0: no asymmetric flow control supported by link partner when auto-negotiation is enabled, this bit reflects link partner ability. (read only). rw 0 5.10 pause 1: flow control supported by link partner 0: no flow control supported by link partner when auto-negotiation is enabled, this bit reflects link partner ability. (read only) ro 0 5.9 100base-t4 1: 100base-t4 supported by link partner 0: 100base-t4 not supported by link partner ro 0 5.8 100base-tx-fd 1: 100base-tx full duplex supported by link partner 0: 100base-tx full duplex not supported by link partner ro 0 5.7 100base-tx 1: 100base-tx half duplex supported by link partner 0: 100base-tx half duplex not supported by link partner ro 0 5.6 10base-t-fd 1: 10base-tx full duplex supported by link partner 0: 10base-tx full duplex not supported by link partner ro 0 5.5 10base-t 1: 10base-tx half duplex supported by link partner 0: 10base-tx half duplex not supported by link partner ro 0 5.[4:0] selector field [00001]=ieee802.3 [00000]=no information from link partner ro 00000 www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 43 track id: jatr-1076-21 rev. 1.3 7.8.9. register6: auto-negotiation expansion table 35. register6: auto-negotiation expansion reg. bit name description mode default 6.[15:5] reserved reserved. ro 0 6.4 parallel detection fault 1: a fault has been detected via the parallel detection function 0: no fault has been detected via the parallel detection function ro 0 6.3 link partner next page ability 1: link partner is next page able 0: link partner is not next page able ro 0 6.2 local next page ability 1: rtl8212/rtl8212n/rtl8211n is next page able (permanently=1) ro 1 6.1 page received 1: a new page has been received 0: a new page has not been received ro/lh 0 6.0 link partner auto-negotiation ability if auto-negotiation is enabled, this bit means: 1: link partner is auto-negotiation able 0: link partner is not auto-negotiation able ro 0 7.8.10. register7: auto-negotiation page transmit register table 36. register7: auto-negotiation page transmit register reg. bit name description mode default 7.15 next page 1: another next page desired 0: no next page to send rw 0 7.14 reserved reserved. ro 0 7.13 message page 1: message page rw 1 7.12 acknowledge 2 1: local device has the ability to comply with the message received 0: local device has no ability to comply with the message received rw 0 7.11 toggle toggle bit. ro 0 7.[10:0] message/unformatted field content of message/unformatted page. rw 0x001 www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 44 track id: jatr-1076-21 rev. 1.3 7.8.11. register8: auto-negotiation li nk partner next page register table 37. register8: auto-negotiation link partner next page register reg. bit name description mode default 8.15 next page r eceived link code word bit 15. ro 0 8.14 acknowledge received link code word bit 14. ro 0 8.13 message page received lin k code word bit 13. ro 0 8.12 acknowledge 2 received lin k code word bit 12. ro 0 8.11 toggle received link code word bit 11. ro 0 8.[10:0] message/unf ormatted field received link c ode word bit 10:0. ro 0x000 7.8.12. register9: 1000base-t control register table 38. register9: 1000base-t control register reg. bit name description mode default 9.[15:13] test mode test mode select. 000: normal mode 001: test mode 1 ? transmit waveform test 010: test mode 2 ? transmit jitter test in master mode 011: test mode 3 ? transmit jitter test in slave mode 100: test mode 4 ? transmitter distortion test 101, 110, 111: reserved rw 000 9.12 master/slave manual configuration enable 1: enable master/slave manual configuration 0: disable master/slave manual configuration rw 0 9.11 master/slave configuration value 1: configure phy as master during master/slave negotiation, only when 9.12 is set to logical one 0: configure phy as slave during master/slave negotiation, only when 9.12 is set to logical one rw 1 9.10 port type 1: multi-port device 0: single-port device rw 1 9.9 1000base-t full duplex 1: advertise phy is 1000base-t full duplex capable 0: advertise phy is not 1000base-t full duplex capable rw 1 9.8 1000base-t half duplex 1: advertise phy is 1000base-t half duplex capable 0: advertise phy is not 1000base-t half duplex capable rw 0 9.[7:0] reserved reserved. rw 0 www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 45 track id: jatr-1076-21 rev. 1.3 7.8.13. register10: 1000base-t status register table 39. register10: 1000base-t status register reg. bit name description mode default 10.15 master/slave configuration fault 1: master/slave configuration fault detected 0: no master/slave configuration fault detected ro 0 10.14 master/slave configuration fault resolution 1: local phy configuration resolved to master 0: local phy configuration resolved to slave ro 0 10.13 local receiver stat us 1: local receiver ok 0: local receiver not ok ro 0 10.12 remote receiver status 1: remote receiver ok 0: remote receiver not ok ro 0 10.11 link partner 1000base-t full duplex 1: link partner is capable of 1000base-t full duplex 0: link partner is not capable of 1000base-t full duplex ro 0 10.10 link partner 1000base-t half duplex 1: link partner is capable of 1000base-t half duplex 0: link partner is not capable of 1000base-t half duplex ro 0 10.[9:8] reserved reserved ro 0 10.[7:0] idle error count idle error counter. the counter stops automatically when it reaches 0xff ro 0 7.8.14. register15: extended status table 40. register15: extended status reg. bit name description mode default 15.15 1000base-x full duplex 0: 1000base-x full duplex not capable ro 0 15.14 1000base-x half duplex 0: 1000base-x half duplex not capable ro 0 15.13 1000base-t full duplex 1: 1000base-t full duplex capable ro 1 15.12 1000base-t half duplex 0: 1000base-t half duplex not capable ro 0 15.[11:0] reserved reserved. ro 0 www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 46 track id: jatr-1076-21 rev. 1.3 8. characteristics 8.1. absolute maximum ratings warning: absolute maximum ratings are limits beyond which permanent damage may be caused to the device, or device re liability may be affecte d. all voltages are specified reference to gnd unless otherwise specified. table 41. absolute maximum ratings parameter min max units storage temperature -10 +125 c supply voltage referenced to vss12 ,avss, avsspll: vdd12, avdd12, svdd12 and avddpll gnd-0.5 +1.32 v supply voltage referenced to avss: avdd18 and svdd18 gnd-0.5 +1.98 v supply voltage referenced to avss: avdd33 and rvdd33 gnd-0.5 +3.63 v digital input voltage gnd-0.5 vddd v dc output voltage gnd-0.5 vddd v 8.2. operating range table 42. operating range parameter min max units ambient operating temperature (ta) 0 +70 c 1.2v vddd, vdda, and vddio supply voltage range 1.14 1.26 v 1.8v vddd, vdda, and vddio supply voltage range 1.71 1.89 v 3.3v vddio supply voltage range 3.14 3.46 v www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 47 track id: jatr-1076-21 rev. 1.3 8.3. dc characteristics table 43. dc characteristics parameter sym condition min typical max units power supply current for analog 1.2v icc 10base-t, idle 10base-t, peak continuous 100% utilization 100base-tx, idle 100base-tx, peak continuous 100% utilization 1000base-t, idle 1000base-t, peak continuous 100% utilization power saving 40 40 40 40 40 40 40 45 45 45 45 45 45 45 50 50 50 50 50 50 50 ma power supply current for digital 1.2v icc 10base-t, idle 10base-t, peak continuous 100% utilization 100base-tx, idle 100base-tx, peak continuous 100% utilization 1000base-t, idle 1000base-t, peak continuous 100% utilization power saving 15 15 105 105 450 470 15 20 20 110 110 460 480 20 30 30 120 120 480 500 30 ma power supply current for analog 1.8v icc 10base-t, idle 10base-t, peak continuous 100% utilization 100base-tx, idle 100base-tx, peak continuous 100% utilization 1000base-t, idle 1000base-t, peak continuous 100% utilization power saving 5 5 90 90 190 190 5 10 10 100 100 200 200 10 15 15 110 110 210 210 15 ma power supply current for analog 3.3v icc 10base-t, idle 10base-t, peak continuous 100% utilization 100base-tx, idle 100base-tx, peak continuous 100% utilization 1000base-t, idle 1000base-t, peak continuous 100% utilization power saving 60 230 50 50 110 110 40 70 240 60 60 120 120 50 80 250 70 70 150 150 60 ma total power consumption for all ports ps 10base-t, idle 10base-t, peak continuous 100% utilization 100base-tx, idle 100base-tx,peak continuous 100% utilization 1000base-t, idle 1000base-t, peak continuous 100% utilization power saving 273 834 393 501 1293 1317 207 327 888 456 564 1362 1386 261 387 948 525 633 1509 1533 321 mw ttl input high voltage v ih - 2.0 - - v ttl input low voltage v il - - - 0.8 v ttl input current i in - -10 - 10 a ttl input capacitance c in - - 3 - pf output high voltage v oh - 2.2 - 2.8 v output low voltage v ol - 0.0 - 0.4 v output three state leakage current | i oz | - - - 10 a www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 48 track id: jatr-1076-21 rev. 1.3 8.4. ac characteristics 8.4.1. mii interface data timing t h t s mrxc/ptxc, mdc mrxd/ptxd[3: 0], mrxdv/ptxen, mcol, mdio figure 21. mii interface reception data timing t cyc t os t oh mrxc/ptxc, mdc mrxd/ptxd[3: 0], mrxdv/ptxen, mcol, mdio figure 22. mii interface transmission data timing www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 49 track id: jatr-1076-21 rev. 1.3 8.4.2. digital timing characteristics table 44. digital timing characteristics parameter sym condition i/o min typ max units mii mode timing 100baset rxc, txc t cyc rxc, txc clock cycle time o - 40 50 ppm - ns 10baset rxc, txc, t cyc rxc, txc clock cycle time o - 400 50 ppm - ns rxd[3:0], rxdv, pcol, output setup time t os output setup time from rxc rising edge to rxd[3:0], rxdv, col o 21 23 25 ns rxd[3:0], rxdv, col, output hold time t oh output hold time from rxc rising edge to rxd[3:0], rxdv, col o 13 15 18 ns txd[3:0], txen, setup time t s txd[3:0], txen to txc rising edge setup time i 4 - - ns txd[3:0], txen, hold time t h txd[3:0], txen to txc rising edge hold time i 2 - - ns gmii mode timing gtxc cycle time t cyc gtxc clock cycle time i - 8 - ns gtxc time high/low t h/l gtxc time high/low i - 4 - ns gtxc rise/fall time t r/f gtxc rise/fall time i - - 1 ns txen, txd setup to gtxc rising t setup txen, txd setup time to gtxc rising edge i 2.5 - - ns txen, txd hold from gtxc rising t hold txen, txd hold time from gtxc rising edge. i 0.5 - - ns rxc t cyc rxc clock cycle time o - 8 - ns rxc time high/low t h/l rxc time high/low o - 4 - ns rxc rise/fall time t r/f rxc rise/fall time i - - 1 ns rxd[7:0],rxdv, col output setup time t os output setup time from rxc rising edge to rxd[0..7], rxdv, col o 2.5 6 - ns rxd[7:0], rxdv, col output hold time t oh output hold time from rxc rising edge to rxd[0..7], rxdv, col o 0.75 1.2 - ns rgmii mode timing rxc t cyc rxc clock cycle time o - 8 - ns data to clock output skew t skew data to clock output skew - -500 0 500 ps rxd[3:0],rxctl output setup time (when rxdly=1) t os output setup time from rxc rising/falling edge to rxd[0..3], rxctl o 1.35 1.6 1.8 ns rxd[3:0], rxctl output hold time (when rxdly=1) t oh output hold time from rxc rising/falling edge to rxd[0..3], rxctl o 2.2 2.4 2.7 ns rgmii signal rising time t r rgmii signals 20% to 80% rising time o - - 0.75 ns rgmii signal rising time t f rgmii signals 80% to 20% falling time o - - 0.75 ns led timing led on time tled on while led blinking 0 - 43 - ms www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 50 track id: jatr-1076-21 rev. 1.3 8.5. thermal characteristics thermal parameters are defined accordi ng to jedec standard jesd 51-2, 51-6: (1) ja (theta ja, thermal resistance from junction to ambient), represents resistance to heat flow from the chip to ambient air. this is an in dex of heat dissipation capability. a lower ja means better thermal performance. ja =(tj - ta) / ph tj is the junction temperature ta is the ambient temperature ph is the power dissipation ? ? ph ta t b ta tc tj (2) jt (psi jt, thermal characterization parameter: junc tion to package top), represents the correlation between the temperature of th e chip and the package top, jt =(tj - tc) / ph, where tj is the junction temperature. (3) jc (theta jc, junction to case thermal resistance), defined as: jc = (tj ? tc) / ph ? ? ph ta t b ta tc tj attach a block with cons tant temperature onto the package. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 51 track id: jatr-1076-21 rev. 1.3 8.5.1. qfn-76 thermal parameters table 45. qfn-76 thermal parameters parameter sym condition air flow 0 m/s air flow 1 m/s air flow 2 m/s units junction to ambient thermal resistance ja 4 layer fr4 pcb 26.3 23.0 22.1 c/w junction to top thermal characterization jt 4 layer fr4 pcb 3.7 - - c/w junction to case thermal resistance jc 4 layer fr4 pcb 11 - - c/w 8.5.2. qfn-76 thermal operating range table 46. qfn-76 thermal operating range parameter sym condition min typ max units junction operating temperature tj - 0 125 c ambient operating temperature ta 4-layer fr4 pcb (without heat sink) 0 25 70 c note: pcb conditions. dimensions: 3" x 4.5". thickness: 1.6mm. 8.5.3. dhs-qfp-128 thermal parameters table 47. dhs-qfp-128 thermal parameters parameter sym condition air flow 0 m/s air flow 1 m/s air flow 2 m/s units junction to ambient thermal resistance ja 4 layer fr4 pcb 26.3 23 21.7 c/w junction to top thermal characterization jt 4 layer fr4 pcb 4.1 - - c/w junction to case thermal resistance jc 4 layer fr4 pcb 12.5 - - c/w 8.5.4. dhs-qfp-128 thermal operating range table 48. dhs-qfp-128 thermal operating range parameter sym condition min typ max units junction operating temperature tj - 0 - 125 c ambient operating temperature ta 4-layer fr4 pcb (without heat sink) 0 25 70 c note: pcb conditions. dimensions: 3.5" x 4". thickness: 1.6mm. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 52 track id: jatr-1076-21 rev. 1.3 9. design and layout guide in order to achieve maximum performance using the rtl8212/rtl8212n/rtl8211n, good design attention is required throughout the design and layout process. the following are some recommendations on how to implement a hi gh performance system. 9.1. general guidelines ? provide a good power source, minimizing noise from switching power s upply circuits (<100mv). ? verify the ability of critical components, e.g. cl ock source and transformer, to meet application requirements. ? use bulk capacitors (4.7 f-10 f) between the power and ground planes. ? use 0.1 f de-coupling capacitors to reduce high-fre quency noise on the power and ground planes. ? keep de-coupling capacitors as close as possi ble to the rtl8212/rtl8212n/rtl8211n (within 200 mil). ? the transformer should be placed as close as po ssible to the rtl8212/rtl8212n/rtl8211n (within 12cm). ? the rj-45 phone jack should be placed as close as possible to the transformer. ? prevent right angles on all traces. 9.2. mii/gmii/rgmii signal layout guidelines ? keep inter-trace spacing with 3 times of trace width, to reduce crosstal k (for example, if the width of the signal trace is 6 mil, the inter-trace spacing should be 18 mil or more). ? for traces longer than 5 inches, guard traces should be placed between signal traces. the guard traces should have many vias to gnd. ? place source termination resisters near output pins. ? route the rgmii traces at 50 ohms impedance. ma tch each rgmii tx and rx group to within 25 mils. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 53 track id: jatr-1076-21 rev. 1.3 9.3. rsgmii signal layout guidelines ? ensure the differential pairs maintain 100 ohm impedance: (5/7/5 for 4 layer pcb: trace width 5 mil, inter-pa ir spacing 7 mil, dielect ric layer thickness 4.4 mil) (9/6/9 for 2 layer pcb: trace width 9 mil, inter-pa ir spacing 6 mil, dielect ric layer thickness 59 mil) ? separate the differential pair and other signals by at least 30mil. ? keep intra-pair length mismatch less than 5mil. ? place ac coupling capacitors near out put pins of differential pairs. ? route both traces of differential pairs symmetrically. ? avoid vias on differential pairs. 9.4. ethernet mdi differential signal layout guidelines ? ensure the differential pairs maintain 100 ohm im pedance and route both traces as identically as possible. ? keep intra-pair length mismatch less than 50mil (from the ic to the transformer and from the transformer to the rj-45). ? avoid vias on differential pairs. ? maintain a 30 mil minimum gap between differential pairs. 9.5. clock circuit ? the clock should be 25m 50ppm with jitter less than 0.5ns. ? if possible, surround the clock by ground tr ace to minimize high-frequency emissions. 9.6. power planes ? divide the power plane into 1.2v digital, 1.2v analog, 1.8v analog and 3.3v analog. ? use 0.1 f decoupling capacitors and bulk capacitors between each power plane and ground plane. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 54 track id: jatr-1076-21 rev. 1.3 9.7. ground plane ? keep the system ground region as one continuous, unbr oken plane that extends from the primary side of the transformer to the rest of the board. ? isolate the avss pin of the rtl8212/rtl8212n/rtl8211n (pin 46, 48 on the qfn-76, and pin 84, 86 on the dhs-qfp-128) with system ground via beads. ? place a moat (gap) between the system ground and chassis ground. ? ensure the chassis ground area is voided at some poi nt such that no ground l oop exists on the chassis ground area. 9.8. transformer options the rtl8212/rtl8212n/rtl8211n uses a transformer with a 1:1 turn ratio. there are many venders offering transformer designs that meet the r tl8212/rtl8212n/rtl8211n?s requirements, e.g., pulse h5014, bothhand gs5014r, and lankom lg-4803-1(r) for the rtl8212/rtl8212n. pulse h5004 and bothhand 24hst1041-2 for the rtl8211n. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 55 track id: jatr-1076-21 rev. 1.3 10. mechanical dimensions 10.1. dhs-qfp-128 dimensions (rtl8212) www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 56 track id: jatr-1076-21 rev. 1.3 10.2. notes for dhs-qfp-128 dimensions (rtl8212) dimension in millimeter dimension in inch symbol min nom max min nom max a ? ? 3.40 ? ? 0.134 a 1 0.25 ? ? 0.010 ? ? a 2 2.50 2.72 2.97 0.101 0.107 0.117 b 0.10 0.20 0.30 0.004 0.008 0.012 c 0.09 ? 0.23 0.004 ? 0.008 d 23.2bsc 0.913bsc d 1 20.00bsc 0.787bsc e 17.20bsc 0.677bsc e 1 14.00bsc 0.551bsc e 0.5bsc 0.20bsc l 0.65 0.88 1.03 0.026 0.035 0.041 l 1 1.60bsc 0.063bsc y ? ? 0.10 ? ? 0.004 0 o ? 12 o 0 o ? 12 o notes 1: dimensions d 1 and e 1 do not include mold protrusion. notes 2: controlling dimension: millimeter (mm). www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 57 track id: jatr-1076-21 rev. 1.3 10.3. qfn-76 dimensions (rtl8211n & rtl8212n) see the mechanical dimensions notes on the next page. www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 58 track id: jatr-1076-21 rev. 1.3 10.4. notes for qfn-76 dimensions (rtl8211n & rtl8212n) www.datasheet.co.kr datasheet pdf - http://www..net/
rtl8212/rtl8212n/rtl8211n datasheet integrated 10/100/1000 single/dual gigabit ethernet transceiver 59 track id: jatr-1076-21 rev. 1.3 11. ordering information table 49. ordering information part number package status rtl8212-gr dhs-qfp-128 in ?green? package production RTL8212N-GR qfn-76 in ?g reen? package production rtl8211n-gr qfn-76 in ?green? package production note: see page 5, 6, and 7 for package identification information. realtek semiconductor corp. headquarters no. 2, innovation road ii hsinchu science park, hsinchu 300, taiwan tel.: +886-3-578-0211. fax: +886-3-577-6047 www.realtek.com.tw www.datasheet.co.kr datasheet pdf - http://www..net/

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